1. Field of the Invention
The present invention relates in general to a hard mask structure for etching a deep trench etch in a substrate, and more particularly, to a boro-silicate glass (BSG) containing multi-layer hard mask structure for etching a deep trench in a substrate.
2. Description of the Related Art
Dynamic random access memory (DRAM) is an important semiconductor device in the information and electronics industry. Most DRAMs presently have one access transistor and one storage capacitor in one DRAM cell. With increased integration, however, 3-D capacitors, such as deep trench capacitors, have become necessary. Typically, 3-D capacitors are disposed in a deep trench formed by etching a silicon substrate. Thereafter, an access transistor is formed overlying the deep trench capacitor to complete a deep trench DRAM cell.
In the formation of integrated circuits, it is often necessary to etch a silicon substrate to form a trench therein. In particular, the trend towards packing more memory cells into a given chip area has led to the development of trench DRAM cells which require deep and narrow apertures in the silicon substrate.
FIGS. 1a to 1c are cross-sections showing a conventional method for etching a deep trench in a silicon substrate. First, in FIG. 1a, a silicon substrate 100 is provided. A pad dielectric layer comprising a thin silicon oxide layer 102 and an overlying silicon nitride layer 104 is formed in the silicon substrate 100. Next, a hard mask layer 106, such as a BSG layer, is formed overlying the pad dielectric layer 102 and 104 for etching the subsequent deep trench. Thereafter, an optional annealing process is performed on the hard mask layer 106. A photoresist pattern layer 108 is formed on the hard mask layer 106 and has an opening 110 to expose the region for etching deep trench.
Next, in FIG. 1b, the hard mask layer 106 and the underlying pad dielectric layer 102 and 104 under the opening 110 are successively etched to form an opening 112 therein, thus exposing the surface of the silicon substrate 100. Next, the photoresist pattern layer 108 is removed.
Finally, in FIG. 1C, the exposed surface of the substrate 100 is etched using the hard mask layer 106 as an etching mask to form a deep trench 114 in the substrate 100. Meanwhile, a portion of the hard mask layer 106 is consumed by etching.
After the deep trench 114 is formed, the hard mask layer 106 is necessary to be removed. The hard mask layer 106 can be removed by vapor hydrofluoric acid (VHF), HF solution, or a buffer oxide etching (BOE) solution. However, after the hard mask layer 106 composed of BSG is annealed, the boron atoms diffuse upwardly. As a result, poor boron atom concentration uniformity is obtained and a practically undoped region (not shown) is formed near the bottom of the hard mask layer 106. Since such an undoped region is difficult to remove by VHF, a remaining hard mask layer 106a is formed on the pad dielectric layer 102 and 104, as shown in FIG. 2a. Additionally, if the hard mask layer 106 is removed by HF solution or BOE solution, there is no remaining hard mask layer. However, the underlying thin silicon oxide layer 102 is undercut, as shown by the arrows in FIG. 2b. As a result, the overlying silicon nitride layer 104 is subject to peeling, thus reducing device yield.
Although no hard mask layer remains without previous annealing of the hard mask layer, various depths and critical dimensions (CDs) result from subsequent deep trench formation in the substrate.